In the processing of information generally, it is often necessary to compare two different signals to accomplish a variety of purposes. The comparison may result in the generation of an error signal representing the difference between the two signals. Circuitry may then respond to the error signal to minimize this difference between the two signals or perform some other function based on this difference.
For example, a phase detector is conventionally used to detect the difference in phase between two signals. The phase detector may be used in a phase-locked loop that, among other components, includes a voltage controlled oscillator (VCO) whose output is a reference frequency signal having a frequency determined by an input control signal. The phase detector receives a stream of data pulse signals, together with the reference frequency signal, which is fed back from the VCO. Any difference in phase between a data pulse signal and the reference frequency signal results in the generation of a phase error signal that is filtered and then used to control the VCO in order to lock the reference frequency signal in phase with the stream of data pulse signals.
Phase-locked loops often incorporate digital or sequential logic phase detectors that generate digital signals corresponding to the difference in phase between the reference frequency signal and the data pulse signal. The digital output from the digital phase detectors typically must be converted to an analog signal for controlling the VCO. Thus, a charge-pump may accompany the digital phase detector to convert the logic states of the phase detector into analog signals suitable for controlling the VCO. A theoretical discussion of prior art charge-pumps can be found in Floyd M. Gardner, "Charge-pump Phase-lock Loops", IEEE TRANSACTIONS ON COMMUNICATIONS, Volume COM-28, Number 11, November 1980. Gardner discusses the operation of charge-pump filters in the phase-locked loop environment.
One problem with prior art charge-pump filters resides in the necessity to include at least two current sources, one to charge up the capacitor in the charge-pump, and one to pull down the charge in the capacitor. Both of the current sources are required to match identically in order to avoid drift in the charge-pump and the introduction of other errors because of unbalanced charge up and charge down. This problem is particularly acute in the implementation of a low order filter for a phase-locked loop. The very low integration rates involved in low order charge pumps can be interfered with by mis-matched current sources.
In addition, prior art filters have been designed with a set bandwidth. However, for many applications, a variable bandwidth charge-pump filter is desirable.
When used as a phase detector, a difficulty arises in the prior art for many types of data pulse streams, such as MFM disk data, in which for a given period of the reference frequency signal from the VCO, no data pulse signals will occur. These missing data pulse signals can cause the phase detector to malfunction.
A prior approach to preventing malfunction due to missing data pulse signals is to arm the phase detector only if a data pulse signal occurs and to disarm the phase detector if a data pulse signal does not occur during the bit time. This technique uses a time delay device which receives in real time the stream of data pulse signals and outputs to the phase detector delayed data pulse signals which are to be compared to the reference frequency signal of the VCO. The phase detector also receives in real time the stream of data pulse signals for arming purposes.
Thus, in operation, the data pulse stream is fed to the input of the time delay device as well as to the phase detector. If a data pulse signal occurs, the phase detector is armed and then, a short time later, receives the same, but delayed, data pulse signal which had been delayed by the time delay device. This delayed data pulse signal is then compared with the reference frequency signal to produce the phase error signal. However, if no data pulse signal occurs during the bit time, the phase detector is not armed, so that it does not operate for phase detection purposes.
One problem with the prior solution is the requirement of a time delay device. In addition to requiring a time delay device which may be expensive, the delay must be precise, so as to have the phase detector properly compare its two input signals. The realization of such a precision time delay is not always easily accomplished. Also, the delay should be equal to one-half the cycle of the nominal frequency of the VCO. Therefore, if the nominal frequency of the VCO is to be changed, which may require using a different VCO in the phase-locked loop, then a new time delay device may be needed in view of the requirement that the delay be equal to one-half the cycle of the nominal frequency. Still furthermore, the arming and disarming of the phase detector has the disadvantage of causing the phase detector to change state between an operative or armed condition and a non-operative or disarmed condition.